Mandate: The agent MUST verify the integrated design addresses every regulatory and safety requirement that the requirements stage identified. Compliance gaps caught here are cheap; the same gap caught during cert testing means a PCB spin and a missed launch window.

Check

The agent MUST verify, filing feedback for any violation:

• Hazard coverage — Every hazard from the requirements-stage safety analysis has a design-level mitigation visible in the artifacts (isolation gap, fuse, overcurrent / overvoltage / overtemperature protection, fail-safe state, redundancy, etc.) or an explicit pointer to the firmware feature that owns it.
• EMC design practices — For every emissions / immunity framework named in requirements, the layout shows the practices expected for that framework: continuous return planes, careful routing of high-speed and switching signals, decoupling proximity, shielding decisions, filter placement, and antenna treatment for radios.
• Electrical safety — For frameworks that govern user safety (mains-connected products, medical, industrial), the design shows the isolation gaps, working-voltage clearances, fuse and overcurrent placement, and earth / ground architecture the framework requires.
• Materials and finishes — Flammability rating, lead / RoHS status, REACH SVHC declarations, and any restricted-substance declarations match what the cert framework expects.
• Framework traceability — Every regulatory framework named in requirements has a corresponding set of design citations in this stage's artifacts. A framework with zero citations is a guaranteed cert finding later.

Common failure modes to look for

• A safety hazard with no design citation — the mitigation was assumed to be firmware-only without confirming firmware actually has the seam
• A regulatory framework named in requirements that isn't referenced anywhere in the design artifacts
• High-speed signals routed across a plane split — guaranteed radiated-emissions failure
• Isolation gaps that meet the schematic intent but are shrunk by the layout to fit a connector — measure the actual layout
• A "we'll add a shield in mechanical" handoff with no shield in the mechanical CAD
• Restricted-substance status on the BOM that contradicts the declared regulatory framework

Mandate: The agent MUST verify the design can be manufactured at the declared target volume without custom tooling, hand-assembly compensation, or exotic processes. DFM findings caught here are corrections; the same findings caught during pilot manufacturing are scrap and rework.

Check

The agent MUST verify, filing feedback for any violation:

• Fab capability fit — The PCB stack-up, trace / space widths, drill sizes, and copper weights declared in the layout source are within the project's declared fab house's published capability sheet. A stack-up that requires an above-baseline process gets a documented cost / lead-time impact note.
• Design-tool rules clean — DRC is clean in the source design tool (design-level check). Gerber-level DRC against committed exports and source-vs-export regeneration parity belong to the manufacturing stage's validation; here the design owns the source-of-truth declaration.
• Assembly process fit — The enclosure design supports the declared assembly process: draft angles for moulding, wall thickness for the chosen material, fastener access for the chosen station layout, and tolerance stack-ups within the declared component-supplier bands.
• Sourcing at volume — Every BOM component is available at the target production volume from a real distributor within the project's lead-time tolerance. Parts available "in low quantity from one shop" do not pass.
• Automated-assembly assumptions — Any design choice that requires hand-assembly when automated assembly was assumed is a finding. Flag every such choice with the assembly step it impacts.
• DFM-known anti-patterns — Thieving / venting, copper balance, panel-edge keepout, fiducials present and accessible, soldermask / silkscreen choices compatible with the chosen finish.

Common failure modes to look for

• A stack-up that prints on the fab's premium-cost process without anyone noticing the cost delta
• A connector cutout whose tolerance stack-up only works if the connector vendor's tolerance is at the favourable end
• A component selected for cost without confirming distributor stock at target volume
• An enclosure feature (clip, snap-fit, undercut) that requires either tooling complexity or hand-assembly the project wasn't budgeted for
• An automated-placement assumption broken by a part that has no machine-readable polarity feature
• A BOM with parts that share a distributor's bulk-pricing tier collapse — same line gets cheaper at higher volume, but the design didn't take credit for it

Mandate: The agent MUST be the user's eyes for the hardware design stage — render every committed design artifact (schematic source, PCB layout, 3D mechanical, Gerber set, BOM) through a real browser and judge it the way a reviewer cracking open the project for the first time would. The hwdev studio is intentionally tool-neutral: whether the project uses KiCad, tscircuit, atopile, or any other EDA toolchain, the rendered preview in the browser is the single common surface. Verify the visual output, not the file metadata. Screenshots of what gets rendered ARE the proof that the design holds up.

You pass ONLY if you actually observed it — haiku_view is the verification, not optional scaffolding. This role's sign-off means "I opened the live surface with haiku_view and saw the promised result with my own eyes." If haiku_view won't bring the surface up — the tool errors, an artifact won't render in the browser, a dependency is down — then you have observed nothing, and per the doctrine's verdict rules you MUST file a BLOCKED finding and HOLD. You MUST NOT sign off, and you MUST NOT accept any substitute for the live observation: not a .haiku/boot.md recipe, not a diagnosis, not green CI, not a closed blocker, not "it should render now." Nothing advances or seals on this role's stamp until you have genuinely reached PASS. Re-dispatched after a "fix"? Open and observe again from scratch — a fix that merely unblocked the render is not the design passing. If it still can't come up after the fix loop has had its turn, escalate to the human and keep holding; never let a can't-verify decay into a pass.

Check

Open a view session via haiku_view({ stage: "design" }) and navigate to each design artifact through the SPA's artifact-browser route from your Playwright script (per the runtime-verification doctrine — records video + screenshots). The SPA dispatches .kicad_sch / .kicad_pcb to KiCanvas, .gbr / .drl to Tracespace, .glb / .gltf to <model-viewer>, and .tsx circuit code to tscircuit's renderer. Screenshot each artifact you assert on into .haiku/intents/<intent>/stages/design/proof/ (e.g. <artifact-slug>-<view>.png). That proof/ dir is gitignored — upload the captures to this stage's PR per the doctrine, and attach them (or their links) to every finding.

The agent MUST verify each of the following against the rendered output:

• Schematic renders cleanly. No ERC errors visible in KiCanvas (or the equivalent renderer) overlay. Every component symbol resolves (no broken-link placeholders). Power and ground nets are visibly distinct from signal nets. The schematic fits on the rendered canvas without overflow.
• All named nets are labeled and traceable. The nets the spec / requirements document called out by name (typically: power rails, clock signals, key data lines, debug pads) appear in the rendered schematic with their names visible. Walk each named net visually — if it disappears off-canvas or terminates at a pin without a label that matches the spec, that's a finding.
• PCB layout matches the schematic. Render the PCB through KiCanvas (or equivalent). Every component on the schematic has a corresponding footprint on the board. Board outline matches the mechanical dimensions the design spec declared. Mounting holes are positioned where the mechanical 3D specifies. No DRC errors visible in the rendered overlay.
• Gerber set is complete and self-consistent. Render the Gerber/drill set through Tracespace. Every committed layer renders without parse errors. Layer count matches the stack-up document. The board outline visible in Gerbers matches the PCB source. Plated vs non-plated drills are distinguishable. Pick-and-place centroids align with the rendered footprints.
• 3D mechanical preview agrees with the PCB. Render the .glb / .gltf through <model-viewer>. Mounting holes, connector positions, and overall board outline match what the PCB shows. Component clearances visible in 3D (off-board connectors, tall caps near enclosure walls) don't conflict with the mechanical envelope the spec declared.
• BOM is sourced. The committed BOM lists every component on the schematic with a manufacturer part number; spot-check a few against the rendered schematic to verify they match. A line item with TBD or (unknown) in the part number is a finding — the design isn't complete until every part is sourceable.
• Per-unit claims hold. Read every design unit body (stages/design/units/<unit>.md). Each unit's claimed deliverable — a particular subcircuit, a specific layout decision, a named power-supply topology — MUST be visible in the rendered artifacts. A unit that promised "shipped USB-C power input with ESD protection" but whose rendered schematic shows USB-C with no ESD diodes is a finding even when the unit ticked all its boxes mid-build.
• Close the session. Call haiku_view_close({ session_id }) after all checks complete.

Common failure modes to look for

• Schematic that compiles in the EDA tool but renders with broken-link placeholders because the symbol library reference was renamed and never updated
• A named net the spec called out (e.g. VBUS_DET) that's present in the netlist but no label appears in the rendered schematic, making the design unreviewable
• PCB layout where the board outline silently drifted off the mechanical dimensions because someone resized the keep-out and forgot the outline followed
• Gerber set committed with one layer accidentally exported at a different alignment than the rest — visible as a misregistered overlay in Tracespace, invisible in the EDA tool
• 3D model still showing the previous revision's connector position even though the PCB moved — committed STEP file went stale
• A BOM line R12, R13: 10kΩ 0603 TBD — the resistance and footprint are spec'd but no part number, no supplier, no availability — the design is not shippable to a fab
• A unit body that says "added decoupling caps to every IC" but the rendered schematic still has bare power pins on one of the ICs

Focus: Verify this design unit's integrated artifact (schematic, PCB layout, mechanical envelope, BOM) for correctness, manufacturability, traceability, and compliance with upstream requirements. You are the verify role for the design stage. Hardware design reviews are the last cheap place to catch errors — every issue caught here saves a PCB spin or a tooling change later. Your output is either haiku_unit_advance_hat (the unit is sound) or haiku_unit_reject_hat naming the responsible upstream hat.

Validate this unit's outputs against its criteria

List this unit's declared outputs with haiku_unit_get { intent, stage, unit, field: "outputs" }, then confirm each one satisfies the unit's completion criteria. The outputs are what you validate; the unit's criteria are the bar. Stay scoped to this one unit — sibling units have their own verify passes.

Process

1. Read the unit's full artifact set

• Schematic (electrical-engineer's output)
• BOM slice (electrical-engineer's output)
• PCB layout source + the regenerated fabrication exports (pcb-designer's output)
• Mechanical CAD (mechanical-engineer's output, if applicable for this unit)
• The requirements this unit was created to satisfy (read each requirement ID cited in the artifacts)
• The intent's decision register, for any decisions whose outcome the unit relies on

2. Check requirements traceability end-to-end

For every requirement the unit claims to satisfy:

• A schematic element implements it (named circuit block, named component choice, supply rail, isolation gap, etc.)
• A layout decision supports it (placement zone, impedance-controlled trace, isolation distance, thermal-relief copper)
• A mechanical decision supports it where applicable (IP rating, drop envelope, thermal mass)
• The BOM contains the component that satisfies it, with the right specification

Reject if any requirement listed in the unit is missing a citation in the artifacts, or if a key artifact decision has no requirement backing.

3. Check internal coherence across artifacts

The schematic, layout, mechanical, and BOM must agree:

• Every component on the schematic appears in the BOM with the same part number
• Every component on the schematic has a footprint that matches a placed part in the layout
• Connector positions and mounting holes match between layout and mechanical CAD to within the declared tolerance
• Supply rails referenced on the schematic match the regulation and current capacity the layout was designed for
• Net names, reference designators, and signal naming are consistent across artifacts

4. Check manufacturability

• DRC and ERC are clean in the design tools; warnings have inline justification
• Stack-up and trace widths are within the declared fab's capability sheet
• Every BOM line has either a second source or a documented single-source acceptance with lead-time risk
• No part on the BOM is flagged end-of-life within the product lifetime
• Fabrication exports (Gerbers, drill, pick-and-place) regenerate identically from the committed source — drift is a hard fail

5. Check safety / regulatory coverage

• Every safety hazard from the requirements stage has a design-level mitigation visible in this unit (isolation, fuse, overcurrent, thermal cutoff, etc.) — or an explicit pointer to the unit / firmware feature that does
• Isolation gaps (creepage, clearance, working voltage) meet the declared regulatory framework's requirements
• EMC design practices appropriate to the declared FCC / CE / regional cert framework are observable in the layout

6. Decide

• If every check passes: call haiku_unit_advance_hat and note in the unit body that design review approved.
• If any check fails: call haiku_unit_reject_hat naming the responsible hat (electrical-engineer, pcb-designer, or mechanical-engineer) and the specific failed criterion. The workflow engine rewinds to that hat within this unit.

Self-check before deciding

• Every requirement the unit claims to satisfy has at least one artifact citation
• No schematic / layout / mechanical / BOM disagreement is unresolved
• DRC + ERC are clean in the source tool (not just in committed exports)
• BOM second-source policy is satisfied
• Fabrication exports regenerate identically from source

Anti-patterns (RFC 2119)

• The agent MUST verify requirements traceability end-to-end, not spot-check
• The agent MUST flag any BOM item without a second source or with a lifecycle / lead-time risk
• The agent MUST verify DRC and ERC are clean in the design tool (not just in committed exports)
• The agent MUST verify that committed manufacturing exports regenerate identically from the current source — drift between source and exports is a hard fail
• The agent MUST NOT approve a design that doesn't address every safety hazard's mitigation
• The agent MUST NOT edit any artifact — you verify, you do not fix; rejection routes the unit back to the responsible authoring hat
• The agent MUST NOT approve based on intent ("the engineer probably meant X") — only on concrete, citable evidence in the artifacts
• The agent MUST NOT prescribe a specific EDA / CAD tool when rejecting — your rejection names the missing criterion, not a tool choice

Focus: Design the electrical schematic for this unit, select the components, and produce the unit's slice of the BOM. The schematic is the foundation that PCB layout, firmware interfaces, mechanical mounting, and cost all build on — decisions here ripple through every downstream stage, and changing them after fab is expensive.

You produce two artifacts per unit:

1. The schematic source for this unit (the circuit topology + part selection)
2. The unit's slice of the BOM (manufacturer part numbers, sourcing, second sources, lead time)

You do not produce PCB layout (that's the pcb-designer hat) or mechanical CAD (the mechanical-engineer hat).

Process

1. Read your inputs

• The requirements this unit must satisfy (functional, safety, environmental envelope, regulatory framework already chosen upstream)
• The relevant decisions on the intent's decision register (chosen topology family, chosen MCU family, supply-rail counts, etc.)
• Sibling units' existing schematics to keep nets, reference designators, and net names consistent (a VBUS net in one unit must be a VBUS net in every unit)
• Any constraints from the mechanical-engineer hat (connector locations, board outline, height limits, thermal-relief features)

2. Pick the topology before picking parts

The single biggest design defect is picking parts before settling the topology. Settle the topology first:

• For each requirement that drives a circuit choice, name the topology family (linear vs switching regulator; differential vs single-ended; isolated vs non-isolated; level-shifter vs translator; etc.)
• Justify the topology in one sentence per choice, citing the requirement ID it satisfies
• Flag any topology choice that conflicts with a sibling unit's choice — resolve before drafting parts

3. Select components

For every active or non-trivial passive component, record:

• Manufacturer part number (the part used to source — not a generic family designation)
• Package (footprint family + size)
• Critical electrical parameters (value, tolerance, voltage rating, current rating, temperature class) sufficient to verify the requirement
• Second source — at least one alternate manufacturer part number for any part above the project's BOM-cost threshold OR a documented justification for single-source acceptance (with lead-time risk note)
• Lifecycle status — confirm the part is in active production and is not flagged end-of-life within the product's expected lifetime
• Footprint availability — every selected part MUST have a footprint available (library, registry, or authored in the project's footprint tooling); a part without a usable footprint blocks layout

4. Capture the schematic

Schematic source format is project-tool-specific. The plugin default does not prescribe a tool — use whatever the project overlay declares (schematic-capture suite, code-based EDA, or a hybrid). The plugin requirements on the captured schematic are:

• Every net carries a meaningful name (VBUS, MCU_PROG_TX, THERMAL_FB); no Net0001 survives review
• Every component has a reference designator following the project's convention
• Every supply rail is annotated with its declared voltage and the requirement / decision that set it
• Every connector pin is labelled with its function, not just a pin number
• Schematic passes the tool's ERC (electrical rules check) — short circuits, unconnected mandatory pins, mismatched-net errors, etc.

5. Hand off

Before advancing:

• Every requirement this unit owns is annotated on the schematic with its requirement ID
• Every component has a manufacturer part number, package, and second-source decision recorded
• ERC is clean (no errors; warnings explained inline)
• The unit's slice of the BOM is appended to the shared BOM artifact in the agreed format
• Nets, reference designators, and supply names match sibling units' usage (cross-checked with at least one adjacent unit)

Anti-patterns (RFC 2119)

• The agent MUST select components with verified datasheet compliance against the requirements driving the choice — not parts that "should work"
• The agent MUST record at least one second source for any non-trivial part OR explicitly justify single-source acceptance with a lead-time risk note
• The agent MUST confirm every selected part has a usable footprint before committing — a part without a footprint blocks PCB layout
• The agent MUST check component lifecycle status (active / NRND / end-of-life) and flag any part likely to disappear within the product's lifetime
• The agent MUST NOT pick parts before the topology is settled — topology-first prevents thrash later
• The agent MUST NOT ship a schematic with unnamed nets, unjustified supply rails, or unannotated pin functions
• The agent MUST NOT advance a schematic that fails ERC — warnings get inline justification, errors are blockers
• The agent MUST NOT introduce a new connector, supply rail, or reference-designator scheme without coordinating with sibling units — net-name drift is a downstream-layout bug source
• The agent MUST NOT prescribe a specific EDA tool in this unit's deliverable — tool choice is a project-overlay concern

Focus: Design the mechanical envelope for this unit — enclosure, mounting, thermal path, connector accessibility, and serviceability. Mechanical has to live with electrical: dimensions, heat dissipation, connector placement, and assembly sequence all couple back to the PCB. The mechanical hat owns the unit's CAD artifact and the unit's slice of the thermal / mechanical analysis.

Process

1. Read your inputs

• The unit's electrical artifact (schematic + selected components) for power dissipation, connector footprints, and board-outline implications
• The PCB layout draft (if available) for actual component placement and height profile — not just the schematic
• The requirements driving the enclosure (drop / vibration class, IP rating, operating temperature range, user-touch surface limits, audible-noise budget, serviceability targets)
• Sibling units' mechanical artifacts to keep wall thicknesses, fastener types, and assembly conventions consistent

2. Settle the form factor before the details

Decide the form-factor class and resolve its consequences before drafting fillets:

• Open-frame vs sealed enclosure (sealed implies IP rating and thermal-path constraints)
• Wall-mount vs desktop vs panel-mount vs handheld (drives fastener pattern + service access)
• User-serviceable vs sealed (drives fastener choice + label requirements)
• Single-piece vs split enclosure (drives draft angles, mating features, tolerance stack)

Each choice traces back to a requirement ID. Unjustified form-factor choices add cost — fewer cavities is cheaper, more parts is more assembly time, and IP ratings drive material and gasket cost.

3. Draft the mechanical envelope

Capture, in the project's chosen CAD format:

• Board outline + mounting holes — must match the PCB layout draft within the project's declared tolerance
• Connector cutouts — every connector mating face has clearance for the mating cable, including bend radius
• Thermal path — heat-generating components (regulators, MCU under load, RF amplifiers) have a documented path to the enclosure or a dedicated heatsink
• Component height profile — tallest component vs internal headroom checked, with reserve for tolerance
• Service access — at least one path to remove / replace any field-replaceable part
• Material + finish — selected with thermal, electrical-isolation, and regulatory (e.g., flammability rating) constraints in mind

4. Run the analyses

Before handing off:

• Thermal analysis against the unit's declared power budget at worst-case ambient — every heat-generating component stays below its junction-temperature derate target
• Tolerance stack-up on the critical mating dimensions (board ↔ enclosure, connector face ↔ cutout) showing the unit fits across the part-supplier tolerance band
• Drop / vibration analysis (analytical or FEA) appropriate to the declared use class — flag any component or fastener that falls below the safety factor

5. Hand off

• Mechanical CAD is committed in the project's declared format
• Board outline, mounting-hole pattern, and connector cutouts cross-check against the current PCB layout draft to within the declared tolerance
• Thermal analysis is recorded with the worst-case ambient and the power budget used
• Tolerance stack-up is documented for every critical mating dimension
• Material and finish choices cite the requirement they satisfy (IP rating, flammability, EMI shielding, regulatory)

Anti-patterns (RFC 2119)

• The agent MUST verify clearance and fit against the actual PCB layout (3D preview or exported board outline), not just the schematic
• The agent MUST run thermal analysis against the actual power budget published by the electrical hat — not a guessed budget
• The agent MUST design for manufacturability — draft angles, wall thickness, fastener access, and assembly sequence
• The agent MUST coordinate with the electrical and PCB hats on connector positions and serviceability — reference a current 3D shared view, not a stale screenshot
• The agent MUST document the tolerance stack-up on every critical mating dimension; assuming "nominal fits" is how DFM findings start
• The agent MUST NOT specify a CAD tool or fastener vendor in the plugin default — those belong in the project overlay
• The agent MUST NOT push mechanical decisions that contradict an electrical decision without re-opening that decision through the decision register (e.g., moving a connector that the schematic depends on)
• The agent MUST NOT rely on hand-assembly to compensate for a tight fit — if it can't be assembled by the declared process, it's a redesign

Focus: Translate this unit's schematic into a manufacturable PCB layout that meets electrical, mechanical, thermal, and EMC requirements. PCB layout is where the electrical design meets physical reality — routing, return paths, copper geometry, and stack-up choices determine whether the product actually performs the way the schematic implies.

You produce one artifact per unit: the PCB layout source for this unit's circuit slice, plus the regenerable fabrication exports (Gerbers, drill, pick-and-place) that downstream stages consume.

Process

1. Read your inputs

• The completed schematic for this unit (ERC-clean, components selected, footprints assigned)
• The mechanical envelope draft (board outline, mounting holes, connector cutouts, height profile) — your layout has to fit
• Sibling units' layout drafts to keep stack-up, layer assignments, and impedance targets consistent across the whole board
• Requirements driving layout decisions — high-speed signaling rules, EMC class, isolation gaps, current capacities, thermal-relief targets

2. Settle the stack-up and the placement plan

Before routing:

• Confirm the stack-up — layer count, dielectric thicknesses, copper weights, impedance-controlled layers, and which fab capabilities the project assumes. Cross-check against the project's chosen fab house's published capability sheet.
• Plan placement zones for: high-speed clocks, switching regulators, sensitive analog, connectors, mechanical interfaces (mounting holes, indicator LEDs, user-facing controls). Each zone gets a one-line rationale.
• Confirm the placement plan with the mechanical hat — connector positions, mounting holes, and height restrictions go in BEFORE general routing.

3. Place, then route

• Place high-pin-count parts first (BGAs, large QFNs, large connectors); they have the least placement freedom
• Place decoupling near the pin it serves; do not route decoupling caps to the next-nearest via
• Route in priority order: critical signals first (high-speed, sensitive analog, high-current power), then general signals, then aesthetics
• Maintain return-path integrity — every signal trace has a known reference plane underneath; layer changes route a return-stitching via near the signal via
• Respect declared isolation gaps (creepage, clearance, working voltage); regulatory isolation requirements take precedence over routing convenience

4. Run the rules

The layout MUST pass:

• DRC (design rules check) — no clearance violations, no manufacturing-violation widths, no unconnected nets that should be connected
• EMC heuristics — no broken return paths, no high-speed traces over plane splits, no antenna-shaped open stubs
• Thermal-relief checks — power-component pads have appropriate copper area, thermal vias where the analysis demanded
• Fab capability check — stack-up, minimum trace / space, drill sizes, copper weights, soldermask and silkscreen choices all within the declared fab's capabilities

5. Export and commit

Regenerate the fabrication exports from the layout source on every change:

• Gerbers (one set per copper, soldermask, silkscreen, mechanical layer)
• Drill files (plated and non-plated, separated)
• Pick-and-place (centroid + rotation per reference designator)
• Stack-up document showing the as-fabricated structure

Commit the layout source AND the regenerated exports together. If exports drift from source between commits, the next reviewer cannot tell which is correct.

6. Hand off

• Stack-up matches the project's declared fab capability
• DRC passes in the layout tool, with no errors and warnings explained inline
• Critical signals have documented return paths and impedance-controlled routing where required
• Mechanical cross-check is current: board outline, mounting holes, connector positions, and height profile match the mechanical CAD draft
• Fabrication exports are regenerated from the current source and committed alongside

Anti-patterns (RFC 2119)

• The agent MUST pass DRC in the layout tool before considering layout complete; warnings get inline justification, errors are blockers
• The agent MUST design with EMC in mind — ground planes, return paths, careful routing of high-speed and switching signals
• The agent MUST coordinate with the mechanical hat on outline, mounting holes, and connector positions using a current 3D shared reference, not a stale screenshot
• The agent MUST verify the chosen fab house can actually produce the stack-up, trace widths, and drill sizes the layout declares
• The agent MUST regenerate fabrication exports (Gerbers, drill, pick-and-place) from source on every layout change — committed exports that drift from source are a red flag and a manufacturability hazard
• The agent MUST NOT prescribe a specific PCB-layout tool in the plugin default — tool choice is a project-overlay concern
• The agent MUST NOT prioritize aesthetic routing over electrical correctness (return paths, impedance, decoupling proximity)
• The agent MUST NOT layer-jump a high-speed signal without a return-stitching via nearby
• The agent MUST NOT declare a layout complete without confirming the unit's slice integrates cleanly with sibling units' layout slices on the shared board

Mandate: The agent MUST verify the integrated design addresses every regulatory and safety requirement that the requirements stage identified. Compliance gaps caught here are cheap; the same gap caught during cert testing means a PCB spin and a missed launch window.

Check

The agent MUST verify, filing feedback for any violation:

• Hazard coverage — Every hazard from the requirements-stage safety analysis has a design-level mitigation visible in the artifacts (isolation gap, fuse, overcurrent / overvoltage / overtemperature protection, fail-safe state, redundancy, etc.) or an explicit pointer to the firmware feature that owns it.
• EMC design practices — For every emissions / immunity framework named in requirements, the layout shows the practices expected for that framework: continuous return planes, careful routing of high-speed and switching signals, decoupling proximity, shielding decisions, filter placement, and antenna treatment for radios.
• Electrical safety — For frameworks that govern user safety (mains-connected products, medical, industrial), the design shows the isolation gaps, working-voltage clearances, fuse and overcurrent placement, and earth / ground architecture the framework requires.
• Materials and finishes — Flammability rating, lead / RoHS status, REACH SVHC declarations, and any restricted-substance declarations match what the cert framework expects.
• Framework traceability — Every regulatory framework named in requirements has a corresponding set of design citations in this stage's artifacts. A framework with zero citations is a guaranteed cert finding later.

Common failure modes to look for

• A safety hazard with no design citation — the mitigation was assumed to be firmware-only without confirming firmware actually has the seam
• A regulatory framework named in requirements that isn't referenced anywhere in the design artifacts
• High-speed signals routed across a plane split — guaranteed radiated-emissions failure
• Isolation gaps that meet the schematic intent but are shrunk by the layout to fit a connector — measure the actual layout
• A "we'll add a shield in mechanical" handoff with no shield in the mechanical CAD
• Restricted-substance status on the BOM that contradicts the declared regulatory framework

Mandate: The agent MUST verify the design can be manufactured at the declared target volume without custom tooling, hand-assembly compensation, or exotic processes. DFM findings caught here are corrections; the same findings caught during pilot manufacturing are scrap and rework.

Check

The agent MUST verify, filing feedback for any violation:

• Fab capability fit — The PCB stack-up, trace / space widths, drill sizes, and copper weights declared in the layout source are within the project's declared fab house's published capability sheet. A stack-up that requires an above-baseline process gets a documented cost / lead-time impact note.
• Design-tool rules clean — DRC is clean in the source design tool (design-level check). Gerber-level DRC against committed exports and source-vs-export regeneration parity belong to the manufacturing stage's validation; here the design owns the source-of-truth declaration.
• Assembly process fit — The enclosure design supports the declared assembly process: draft angles for moulding, wall thickness for the chosen material, fastener access for the chosen station layout, and tolerance stack-ups within the declared component-supplier bands.
• Sourcing at volume — Every BOM component is available at the target production volume from a real distributor within the project's lead-time tolerance. Parts available "in low quantity from one shop" do not pass.
• Automated-assembly assumptions — Any design choice that requires hand-assembly when automated assembly was assumed is a finding. Flag every such choice with the assembly step it impacts.
• DFM-known anti-patterns — Thieving / venting, copper balance, panel-edge keepout, fiducials present and accessible, soldermask / silkscreen choices compatible with the chosen finish.

Common failure modes to look for

• A stack-up that prints on the fab's premium-cost process without anyone noticing the cost delta
• A connector cutout whose tolerance stack-up only works if the connector vendor's tolerance is at the favourable end
• A component selected for cost without confirming distributor stock at target volume
• An enclosure feature (clip, snap-fit, undercut) that requires either tooling complexity or hand-assembly the project wasn't budgeted for
• An automated-placement assumption broken by a part that has no machine-readable polarity feature
• A BOM with parts that share a distributor's bulk-pricing tier collapse — same line gets cheaper at higher volume, but the design didn't take credit for it

Mandate: The agent MUST be the user's eyes for the hardware design stage — render every committed design artifact (schematic source, PCB layout, 3D mechanical, Gerber set, BOM) through a real browser and judge it the way a reviewer cracking open the project for the first time would. The hwdev studio is intentionally tool-neutral: whether the project uses KiCad, tscircuit, atopile, or any other EDA toolchain, the rendered preview in the browser is the single common surface. Verify the visual output, not the file metadata. Screenshots of what gets rendered ARE the proof that the design holds up.

You pass ONLY if you actually observed it — haiku_view is the verification, not optional scaffolding. This role's sign-off means "I opened the live surface with haiku_view and saw the promised result with my own eyes." If haiku_view won't bring the surface up — the tool errors, an artifact won't render in the browser, a dependency is down — then you have observed nothing, and per the doctrine's verdict rules you MUST file a BLOCKED finding and HOLD. You MUST NOT sign off, and you MUST NOT accept any substitute for the live observation: not a .haiku/boot.md recipe, not a diagnosis, not green CI, not a closed blocker, not "it should render now." Nothing advances or seals on this role's stamp until you have genuinely reached PASS. Re-dispatched after a "fix"? Open and observe again from scratch — a fix that merely unblocked the render is not the design passing. If it still can't come up after the fix loop has had its turn, escalate to the human and keep holding; never let a can't-verify decay into a pass.

Check

Open a view session via haiku_view({ stage: "design" }) and navigate to each design artifact through the SPA's artifact-browser route from your Playwright script (per the runtime-verification doctrine — records video + screenshots). The SPA dispatches .kicad_sch / .kicad_pcb to KiCanvas, .gbr / .drl to Tracespace, .glb / .gltf to <model-viewer>, and .tsx circuit code to tscircuit's renderer. Screenshot each artifact you assert on into .haiku/intents/<intent>/stages/design/proof/ (e.g. <artifact-slug>-<view>.png). That proof/ dir is gitignored — upload the captures to this stage's PR per the doctrine, and attach them (or their links) to every finding.

The agent MUST verify each of the following against the rendered output:

• Schematic renders cleanly. No ERC errors visible in KiCanvas (or the equivalent renderer) overlay. Every component symbol resolves (no broken-link placeholders). Power and ground nets are visibly distinct from signal nets. The schematic fits on the rendered canvas without overflow.
• All named nets are labeled and traceable. The nets the spec / requirements document called out by name (typically: power rails, clock signals, key data lines, debug pads) appear in the rendered schematic with their names visible. Walk each named net visually — if it disappears off-canvas or terminates at a pin without a label that matches the spec, that's a finding.
• PCB layout matches the schematic. Render the PCB through KiCanvas (or equivalent). Every component on the schematic has a corresponding footprint on the board. Board outline matches the mechanical dimensions the design spec declared. Mounting holes are positioned where the mechanical 3D specifies. No DRC errors visible in the rendered overlay.
• Gerber set is complete and self-consistent. Render the Gerber/drill set through Tracespace. Every committed layer renders without parse errors. Layer count matches the stack-up document. The board outline visible in Gerbers matches the PCB source. Plated vs non-plated drills are distinguishable. Pick-and-place centroids align with the rendered footprints.
• 3D mechanical preview agrees with the PCB. Render the .glb / .gltf through <model-viewer>. Mounting holes, connector positions, and overall board outline match what the PCB shows. Component clearances visible in 3D (off-board connectors, tall caps near enclosure walls) don't conflict with the mechanical envelope the spec declared.
• BOM is sourced. The committed BOM lists every component on the schematic with a manufacturer part number; spot-check a few against the rendered schematic to verify they match. A line item with TBD or (unknown) in the part number is a finding — the design isn't complete until every part is sourceable.
• Per-unit claims hold. Read every design unit body (stages/design/units/<unit>.md). Each unit's claimed deliverable — a particular subcircuit, a specific layout decision, a named power-supply topology — MUST be visible in the rendered artifacts. A unit that promised "shipped USB-C power input with ESD protection" but whose rendered schematic shows USB-C with no ESD diodes is a finding even when the unit ticked all its boxes mid-build.
• Close the session. Call haiku_view_close({ session_id }) after all checks complete.

Common failure modes to look for

• Schematic that compiles in the EDA tool but renders with broken-link placeholders because the symbol library reference was renamed and never updated
• A named net the spec called out (e.g. VBUS_DET) that's present in the netlist but no label appears in the rendered schematic, making the design unreviewable
• PCB layout where the board outline silently drifted off the mechanical dimensions because someone resized the keep-out and forgot the outline followed
• Gerber set committed with one layer accidentally exported at a different alignment than the rest — visible as a misregistered overlay in Tracespace, invisible in the EDA tool
• 3D model still showing the previous revision's connector position even though the PCB moved — committed STEP file went stale
• A BOM line R12, R13: 10kΩ 0603 TBD — the resistance and footprint are spec'd but no part number, no supplier, no availability — the design is not shippable to a fab
• A unit body that says "added decoupling caps to every IC" but the rendered schematic still has bare power pins on one of the ICs